1. Field of the Invention
The present invention relates to a field effect type semiconductor device provided with a body region that receives field effect of a gate electrode and a drift region arranged below the body region. More particularly, it relates to a high withstand voltage field effect type semiconductor device that achieves to enhance withstand-ability against higher voltage without sacrificing ON-voltage.
2. Description of Related Art
There have conventionally been used field effect type semiconductor devices for power devices (for example, JP Laid-open Patent Publication 09-283754, and the like). This type of field effect type semiconductor device has structure such as shown in FIG. 20, in general. A sectional view of a portion E—E is substantially same as FIG. 1 of which numberings are changed from “1**” to “9**”. Hereinafter, numbering should be interpreted like that when FIG. 1 is referred in the description of related art. FIG. 20 is a sectional view of a portion A—A in FIG. 1. This field effect type semiconductor device has trench type gate electrodes 906. Roughly speaking, the field-effect-type semiconductor device is structured such that emitter regions (900, 904) and gate electrodes 906 are arranged at a surface side of its semiconductor substrate (upper side in FIG. 20) and a collector region 901 is arranged at the reverse side (lower side in FIG. 20).
That is, there are arranged trench type gate electrodes 906, P+ emitter regions 900, and N+ emitter regions 904 at the surface side of the semiconductor substrate. Each gate electrode 906 is insulated from the semiconductor substrate by a gate dielectric 905 and an interlayer dielectric 907. An emitter electrode 909 is arranged above the interlayer dielectric 907. The emitter electrode 909 is in contact with the semiconductor substrate at contact openings 908, zonal portions in parallel to gate electrodes 906 in FIG. 1. Therefore, the emitter electrode 909 is in contact to both P+ emitter regions 900 and N+ emitter regions 904. P channel regions 903 are arranged below those emitter regions. Bottom level of P body regions 903 is shallower than that of gate electrodes 906.
An N drift region 902 is formed below P channel regions 903. Most part of the N drift region 902 is deeper than the bottom level of gate electrodes 906 and extends to almost entire plane of the semiconductor substrate. A P+ collector region 901 is arranged further below the N drift region 902. A collector electrode 910 is formed in contact with the bottom portion of the P+ collector region 901. In this field effect type semiconductor device, field effect is induced at P body regions 903 by applying voltage to gate electrodes 906 to control conduction between the emitter electrode 909 and the collector electrode 910.
However, the above-described conventional field-effect-type semiconductor device has had following problems. That is, in case it is intended to enhance withstand-ability against high voltage between an emitter and a collector, thickness of the N drift region 902 (represented as “T” in FIG. 20) must be made thick. Thereby, an electric field of the P body region 903 and N drift regions 902 is relaxed and withstand-ability against high voltage can be achieved. However in this case, parasitic resistance of N drift region 902 is large in proportion to thickness. This also means ON-voltage is high in proportion to it. Furthermore, amount of carriers remaining in the N drift region 902 after switch-OFF is large in proportion to it. This means turn-OFF time is long. Lengthy turn-OFF time itself means poor operating ability and large switching loss. Therefore, there is a fear of device destruction due to heat. For avoiding such device destruction, device size had to be large so as to decrease current concentration.